%0 Conference Paper %1 conf/vlsid/RajanF98 %A Rajan, Sreeranga P. %A Fujita, Masahiro %B VLSI Design %D 1998 %I IEEE Computer Society %K dblp %P 552-557 %T Integration of High-Level Modeling, Formal Verification, and High-Level Synthesis in ATM Switch Design. %U http://dblp.uni-trier.de/db/conf/vlsid/vlsid1998.html#RajanF98 %@ 0-8186-8224-8

@inproceedings{conf/vlsid/RajanF98, added-at = {2023-03-24T00:00:00.000+0100}, author = {Rajan, Sreeranga P. and Fujita, Masahiro}, biburl = {https://www.bibsonomy.org/bibtex/25f1f8e417c375dcbee0dbb399fe603af/dblp}, booktitle = {VLSI Design}, crossref = {conf/vlsid/1998}, ee = {https://doi.ieeecomputersociety.org/10.1109/ICVD.1998.646663}, interhash = {f6aa25368305084ab2d3393aa8bbbc55}, intrahash = {5f1f8e417c375dcbee0dbb399fe603af}, isbn = {0-8186-8224-8}, keywords = {dblp}, pages = {552-557}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T05:47:35.000+0200}, title = {Integration of High-Level Modeling, Formal Verification, and High-Level Synthesis in ATM Switch Design.}, url = {http://dblp.uni-trier.de/db/conf/vlsid/vlsid1998.html#RajanF98}, year = 1998 }