%0 Conference Paper %1 conf/date/PozzoniFMPP23 %A Pozzoni, Luca Ezio %A Ferrandi, Fabrizio %A Mendola, Loris %A Palazzo, Alfio Antonino %A Pappalardo, Francesco %B DATE %D 2023 %I IEEE %K dblp %P 1-6 %T Using High-Level Synthesis to model System Verilog procedural timing controls. %U http://dblp.uni-trier.de/db/conf/date/date2023.html#PozzoniFMPP23 %@ 978-3-9819263-7-8

@inproceedings{conf/date/PozzoniFMPP23, added-at = {2023-11-12T00:00:00.000+0100}, author = {Pozzoni, Luca Ezio and Ferrandi, Fabrizio and Mendola, Loris and Palazzo, Alfio Antonino and Pappalardo, Francesco}, biburl = {https://www.bibsonomy.org/bibtex/28df6b44b342fb0cbe490e546b7e3b0a5/dblp}, booktitle = {DATE}, crossref = {conf/date/2023}, ee = {https://doi.org/10.23919/DATE56975.2023.10136907}, interhash = {f6bd0da9ff703fdadce0a9f4927eed6b}, intrahash = {8df6b44b342fb0cbe490e546b7e3b0a5}, isbn = {978-3-9819263-7-8}, keywords = {dblp}, pages = {1-6}, publisher = {IEEE}, timestamp = {2024-04-09T12:36:17.000+0200}, title = {Using High-Level Synthesis to model System Verilog procedural timing controls.}, url = {http://dblp.uni-trier.de/db/conf/date/date2023.html#PozzoniFMPP23}, year = 2023 }