Author of the publication

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Using High-Level Synthesis to model System Verilog procedural timing controls.

L. Pozzoni, F. Ferrandi, L. Mendola, A. Palazzo, and F. Pappalardo. DATE, page 1-6. IEEE, (2023)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Fabrizio Catanese

Fabrizio Gabbiani

Fabrizio Gabrielli

Fabrizio Lindner

Fabrizio Arosio

Other publications of authors with the same name

Symbolic optimization of interacting controllers based onredundancy identification and removal.F. Ferrandi, F. Fummi, E. Macii, M. Poncino, and D. Sciuto. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 19 (7): 760-772 (2000)An Expert Solution to Functional Testability Analysis of VLSI Circuits.M. Bombana, G. Buonanno, P. Cavalloro, F. Ferrandi, D. Sciuto, and G. Zaza. SEKE, page 263-265. Knowledge Systems Institute, (1993)Reduction of Fault Detection Costs through Testable Design of Sequential Architectures with Signal Feedbacks.M. Bombana, G. Buonanno, P. Cavalloro, F. Ferrandi, D. Sciuto, and G. Zaza. DFT, page 223-230. IEEE Computer Society, (1993)Symbolic Optimization of FSM Networks Based on Sequential ATPG Techniques.F. Ferrandi, F. Fummi, E. Macii, M. Poncino, and D. Sciuto. DAC, page 467-470. ACM Press, (1996)A design methodology to implement memory accesses in high-level synthesis.C. Pilato, F. Ferrandi, and D. Sciuto. CODES+ISSS, page 49-58. ACM, (2011)An Interrupt Controller for FPGA-based Multiprocessors.A. Tumeo, M. Branca, L. Camerini, M. Monchiero, G. Palermo, F. Ferrandi, and D. Sciuto. ICSAMOS, page 82-87. IEEE, (2007)Hardware DWT accelerator for MultiProcessor System-on-Chip on FPGA.S. Borgio, D. Bosisio, F. Ferrandi, M. Monchiero, M. Santambrogio, D. Sciuto, and A. Tumeo. ICSAMOS, page 107-114. IEEE, (2006)Code Transformations Based on Speculative SDC Scheduling.M. Lattuada, and F. Ferrandi. ICCAD, page 71-77. IEEE, (2015)High Level Synthesis of RDF Queries for Graph Analytics.V. Castellana, M. Minutoli, A. Morari, A. Tumeo, M. Lattuada, and F. Ferrandi. ICCAD, page 323-330. IEEE, (2015)SODA Synthesizer: An Open-Source, Multi-Level, Modular, Extensible Compiler from High-Level Frameworks to Silicon.N. Agostini, A. Limaye, M. Minutoli, V. Castellana, J. Manzano, A. Tumeo, S. Curzel, and F. Ferrandi. ICCAD, page 18:1-18:7. ACM, (2022)

BibSonomy

Disambiguation of "Ferrandi, Fabrizio"

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Using High-Level Synthesis to model System Verilog procedural timing controls.

Please choose a person to relate this publication to

Fabrizio Catanese

Fabrizio Gabbiani

Fabrizio Gabrielli

Fabrizio Lindner

Fabrizio Arosio

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Ferrandi, Fabrizio"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Using High-Level Synthesis to model System Verilog procedural timing controls.

Please choose a person to relate this publication to

Fabrizio Catanese

Fabrizio Gabbiani

Fabrizio Gabrielli

Fabrizio Lindner

Fabrizio Arosio

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Using High-Level Synthesis to model System Verilog procedural timing controls.