%0 Conference Paper %1 conf/asicon/GeZ0W017 %A Ge, Xiang %A Zhu, Hengliang %A Yang, Fan %A Wang, Lingli %A Zeng, Xuan %B ASICON %D 2017 %E Qin, Yajie %E Hong, Zhiliang %E Tang, Ting-Ao %I IEEE %K dblp %P 259-262 %T Parallel sparse LU decomposition using FPGA with an efficient cache architecture. %U http://dblp.uni-trier.de/db/conf/asicon/asicon2017.html#GeZ0W017 %@ 978-1-5090-6625-4

@inproceedings{conf/asicon/GeZ0W017, added-at = {2018-01-17T00:00:00.000+0100}, author = {Ge, Xiang and Zhu, Hengliang and Yang, Fan and Wang, Lingli and Zeng, Xuan}, biburl = {https://www.bibsonomy.org/bibtex/254c160e6e043ab74e3f4b37d98677aff/dblp}, booktitle = {ASICON}, crossref = {conf/asicon/2017}, editor = {Qin, Yajie and Hong, Zhiliang and Tang, Ting-Ao}, ee = {https://doi.org/10.1109/ASICON.2017.8252462}, interhash = {fb9b7bf7af50c1d11252fe49f8f75f1c}, intrahash = {54c160e6e043ab74e3f4b37d98677aff}, isbn = {978-1-5090-6625-4}, keywords = {dblp}, pages = {259-262}, publisher = {IEEE}, timestamp = {2018-01-18T11:40:09.000+0100}, title = {Parallel sparse LU decomposition using FPGA with an efficient cache architecture.}, url = {http://dblp.uni-trier.de/db/conf/asicon/asicon2017.html#GeZ0W017}, year = 2017 }