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Parallel sparse LU decomposition using FPGA with an efficient cache architecture.

X. Ge, H. Zhu, F. Yang, L. Wang, and X. Zeng. ASICON, page 259-262. IEEE, (2017)

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Haibo Xuan

Zhengrong Xuan

Yue Xuan

Chaoting Xuan

Yimin Xuan

Other publications of authors with the same name

Wavelet method for high-speed clock tree simulation.X. Li, X. Zeng, D. Zhou, and X. Ling. ISCAS (1), page 177-180. IEEE, (2002)A parallel sparse linear system solver for large-scale circuit simulation based on Schur Complement.L. Qian, D. Zhou, X. Zeng, F. Yang, and S. Wang. ASICON, page 1-4. IEEE, (2013)Fast compressive sensing reconstruction algorithm on FPGA using Orthogonal Matching Pursuit.Z. Yu, J. Su, F. Yang, Y. Su, X. Zeng, D. Zhou, and W. Shi. ISCAS, page 249-252. IEEE, (2016)Direct Nonlinear Order Reduction with Variational Analysis.L. Feng, X. Zeng, C. Chiang, D. Zhou, and Q. Fang. DATE, page 1316-1321. IEEE Computer Society, (2004)Efficient spectral graph sparsification via Krylov-subspace based spectral perturbation analysis.S. Zhang, F. Yang, X. Zeng, D. Zhou, S. Li, and X. Hu. ISCAS, page 1-4. IEEE, (2017)PulsePrint: Single-arm-ECG biometric human identification using deep learning.Q. Zhang, D. Zhou, and X. Zeng. UEMCON, page 452-456. IEEE, (2017)A novel wavelet method for noise analysis of nonlinear circuits.X. Zeng, B. Liu, J. Tao, C. Chiang, and D. Zhou. ASP-DAC, page 471-476. ACM Press, (2005)C-YES: An Efficient Parametric Yield Estimation Approach for Analog and Mixed-Signal Circuits Based on Multicorner-Multiperformance Correlations.W. Zeng, H. Zhu, X. Zeng, D. Zhou, R. Liu, and X. Li. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 36 (6): 899-912 (2017)A yield-enhanced global optimization methodology for analog circuit based on extreme value theory.M. Li, G. Huang, X. Wu, L. Qian, X. Zeng, and D. Zhou. Sci. China Inf. Sci., 59 (8): 082401:1-082401:16 (2016)An Efficient FPGA Implementation of Orthogonal Matching Pursuit With Square-Root-Free QR Decomposition.X. Ge, F. Yang, H. Zhu, X. Zeng, and D. Zhou. IEEE Trans. Very Large Scale Integr. Syst., 27 (3): 611-623 (2019)

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Disambiguation of "Zeng, Xuan"

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Parallel sparse LU decomposition using FPGA with an efficient cache architecture.

Please choose a person to relate this publication to

Haibo Xuan

Zhengrong Xuan

Yue Xuan

Chaoting Xuan

Yimin Xuan

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Zeng, Xuan"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Parallel sparse LU decomposition using FPGA with an efficient cache architecture.

Please choose a person to relate this publication to

Haibo Xuan

Zhengrong Xuan

Yue Xuan

Chaoting Xuan

Yimin Xuan

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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URL
DOI
BibTeX
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APA
Chicago
DIN 1505
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Parallel sparse LU decomposition using FPGA with an efficient cache architecture.