Design styles of Asymmetric nMOS and their Simulation
K. Rane. International Journal on Recent and Innovation Trends in Computing and Communication, 3 (3):
1129--1131(March 2015)
DOI: 10.17762/ijritcc2321-8169.150352
Abstract
Scaling down of the MOSFET has been done extensively to meet the need for high speed devices. Symmetric MOSFET with LDD structure could not mitigate the short channel effects, as the device was scaled down to deep sub-micrometer regime. Asymmetric MOSFET design styles were thus adopted to achieve increased device speed. In this paper, two asymmetric MOSFETs are designed and simulated using device simulator (SILVACO) - one with LDD at drain side only and second with unequal junction depths.
%0 Journal Article
%1 Ramesh_2015
%A Rane, Kimaya Ramesh
%D 2015
%I Auricle Technologies, Pvt., Ltd.
%J International Journal on Recent and Innovation Trends in Computing and Communication
%K (LDD) Si-SiO2 channel doped drain effects electron hot impact interface ionization lightly short
%N 3
%P 1129--1131
%R 10.17762/ijritcc2321-8169.150352
%T Design styles of Asymmetric nMOS and their Simulation
%U http://dx.doi.org/10.17762/ijritcc2321-8169.150352
%V 3
%X Scaling down of the MOSFET has been done extensively to meet the need for high speed devices. Symmetric MOSFET with LDD structure could not mitigate the short channel effects, as the device was scaled down to deep sub-micrometer regime. Asymmetric MOSFET design styles were thus adopted to achieve increased device speed. In this paper, two asymmetric MOSFETs are designed and simulated using device simulator (SILVACO) - one with LDD at drain side only and second with unequal junction depths.
@article{Ramesh_2015,
abstract = {Scaling down of the MOSFET has been done extensively to meet the need for high speed devices. Symmetric MOSFET with LDD structure could not mitigate the short channel effects, as the device was scaled down to deep sub-micrometer regime. Asymmetric MOSFET design styles were thus adopted to achieve increased device speed. In this paper, two asymmetric MOSFETs are designed and simulated using device simulator (SILVACO) - one with LDD at drain side only and second with unequal junction depths.},
added-at = {2015-08-06T09:12:16.000+0200},
author = {Rane, Kimaya Ramesh},
biburl = {https://www.bibsonomy.org/bibtex/20061cb4b3e8a5e9020c316f7c36f271a/ijritcc},
doi = {10.17762/ijritcc2321-8169.150352},
interhash = {fd9214f622f561c93663cd74dcdc1c34},
intrahash = {0061cb4b3e8a5e9020c316f7c36f271a},
journal = {International Journal on Recent and Innovation Trends in Computing and Communication},
keywords = {(LDD) Si-SiO2 channel doped drain effects electron hot impact interface ionization lightly short},
month = {march},
number = 3,
pages = {1129--1131},
publisher = {Auricle Technologies, Pvt., Ltd.},
timestamp = {2015-08-06T09:12:16.000+0200},
title = {Design styles of Asymmetric {nMOS} and their Simulation},
url = {http://dx.doi.org/10.17762/ijritcc2321-8169.150352},
volume = 3,
year = 2015
}