%0 Journal Article %1 journals/tcas/ShiehCLW09 %A Shieh, Ming-Der %A Chen, Jun-Hong %A Lin, Wen-Ching %A Wu, Hao-Hsuan %D 2009 %J IEEE Trans. Circuits Syst. I Regul. Pap. %K dblp %N 9 %P 2009-2019 %T A New Algorithm for High-Speed Modular Multiplication Design. %U http://dblp.uni-trier.de/db/journals/tcas/tcasI56.html#ShiehCLW09 %V 56-I

@article{journals/tcas/ShiehCLW09, added-at = {2020-05-22T00:00:00.000+0200}, author = {Shieh, Ming-Der and Chen, Jun-Hong and Lin, Wen-Ching and Wu, Hao-Hsuan}, biburl = {https://www.bibsonomy.org/bibtex/220c7f6b7bd5d87fe1d917604577b2ba4/dblp}, ee = {https://doi.org/10.1109/TCSI.2008.2011585}, interhash = {2a4770753a844736d47f9e77d2154fc6}, intrahash = {20c7f6b7bd5d87fe1d917604577b2ba4}, journal = {IEEE Trans. Circuits Syst. I Regul. Pap.}, keywords = {dblp}, number = 9, pages = {2009-2019}, timestamp = {2020-05-23T12:33:43.000+0200}, title = {A New Algorithm for High-Speed Modular Multiplication Design.}, url = {http://dblp.uni-trier.de/db/journals/tcas/tcasI56.html#ShiehCLW09}, volume = {56-I}, year = 2009 }