%0 Journal Article %1 journals/tdsc/PolianHRB11 %A Polian, Ilia %A Hayes, John P. %A Reddy, Sudhakar M. %A Becker, Bernd %D 2011 %J IEEE Trans. Dependable Secur. Comput. %K dblp %N 4 %P 537-547 %T Modeling and Mitigating Transient Errors in Logic Circuits. %U http://dblp.uni-trier.de/db/journals/tdsc/tdsc8.html#PolianHRB11 %V 8

@article{journals/tdsc/PolianHRB11, added-at = {2023-03-21T00:00:00.000+0100}, author = {Polian, Ilia and Hayes, John P. and Reddy, Sudhakar M. and Becker, Bernd}, biburl = {https://www.bibsonomy.org/bibtex/2c31ef5bddd924a57d78cf18441c21f0f/dblp}, ee = {http://doi.ieeecomputersociety.org/10.1109/TDSC.2010.26}, interhash = {48704b095c6555d795e99cca6798da0b}, intrahash = {c31ef5bddd924a57d78cf18441c21f0f}, journal = {IEEE Trans. Dependable Secur. Comput.}, keywords = {dblp}, number = 4, pages = {537-547}, timestamp = {2024-04-09T06:53:58.000+0200}, title = {Modeling and Mitigating Transient Errors in Logic Circuits.}, url = {http://dblp.uni-trier.de/db/journals/tdsc/tdsc8.html#PolianHRB11}, volume = 8, year = 2011 }