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Disambiguation of "Hayes, John P."

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Modeling and Mitigating Transient Errors in Logic Circuits.

, , , and . IEEE Trans. Dependable Secur. Comput., 8 (4): 537-547 (2011)

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Matthew John Hayes

John P Burrows

John P Brown

John P Broussard

John P Dickson

 

Other publications of authors with the same name

Hierarchical test generation using precomputed tests for modules., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 9 (6): 594-603 (1990)Connective Fault Tolerance in Multiple-Bus Systems., and . IEEE Trans. Parallel Distributed Syst., 8 (6): 574-586 (1997)Retraining and Regularization to Optimize Neural Networks for Stochastic Computing., , , and . ISVLSI, page 246-251. IEEE, (2020)Survey of Stochastic Computing., and . ACM Trans. Embed. Comput. Syst., 12 (2s): 92:1-92:19 (2013)An Array Layout Methodology for VLlSI Circuits., and . IEEE Trans. Computers, 35 (12): 1055-1067 (1986)Structural fault tolerance in VLSI-based systems., and . Great Lakes Symposium on VLSI, page 50-55. IEEE, (1994)A Nand Model ror Fault Diagnosis in Combinational Logic Networks.. IEEE Trans. Computers, 20 (12): 1496-1506 (1971)CLIP: An Optimizing Layout Generator for Two-Dimensional CMOS Cells., and . DAC, page 452-455. ACM Press, (1997)Test-Set Preserving Logic Transformations., and . DAC, page 454-458. IEEE Computer Society Press, (1992)On the Role of Sequential Circuits in Stochastic Computing., and . ACM Great Lakes Symposium on VLSI, page 475-478. ACM, (2017)