%0 Conference Paper %1 WuZha17High %A Wu, Ephrem %A Zhang, Xiaoqian %A Berman, David %A Cho, Inkeun %B Field Programmable Logic and Applications (FPL), 2017 27th International Conference on %D 2017 %K acceleration convolution fpga hardware matrix_vector_mult sdaccel %P 1--4 %T A high-throughput reconfigurable processing array for neural networks %U https://ieeexplore.ieee.org/abstract/document/8056794

@inproceedings{WuZha17High, added-at = {2019-01-25T13:51:44.000+0100}, author = {Wu, Ephrem and Zhang, Xiaoqian and Berman, David and Cho, Inkeun}, biburl = {https://www.bibsonomy.org/bibtex/2f7c4e4cbfe5ef7720e57903f0ab66ced/loroch}, booktitle = {Field Programmable Logic and Applications (FPL), 2017 27th International Conference on}, interhash = {37f085caf2b98547f5ea112de99e1597}, intrahash = {f7c4e4cbfe5ef7720e57903f0ab66ced}, keywords = {acceleration convolution fpga hardware matrix_vector_mult sdaccel}, organization = {IEEE}, pages = {1--4}, timestamp = {2019-01-25T13:51:44.000+0100}, title = {A high-throughput reconfigurable processing array for neural networks}, url = {https://ieeexplore.ieee.org/abstract/document/8056794}, year = 2017 }