tag :: fpga | BibSonomy

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1Researchers run high-performing large language model on the energy needed to power a lightbulb
https://news.ucsc.edu/2024/06/matmul-free-llm.html
9 days ago by @taein.kim
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2[2406.02528] Scalable MatMul-free Language Modeling
https://arxiv.org/abs/2406.02528
9 days ago by @taein.kim
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1When network is faster than browser cache (2020) | Hacker News
https://web.archive.org/web/20220630205507/https://news.ycombinator.com/item?id=31922762
2 years ago by @bshanks
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1FPGA Interchange format to enable interoperable FPGA tooling | Hacker News
https://news.ycombinator.com/item?id=30317317
2 years ago by @bshanks
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1References and Reading List
http://fpgacpu.ca/fpga/reading.html
3 years ago by @bshanks
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book
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1FPGA Design Elements
http://fpgacpu.ca/fpga/index.html
3 years ago by @bshanks
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lib
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1fpgacpu.ca
http://fpgacpu.ca/
3 years ago by @bshanks
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1Yosys and open source FPGA toolchains. I think FPGA are vastly underrated and ha... | Hacker News
https://news.ycombinator.com/item?id=26783440
3 years ago by @bshanks
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1BladeRF-wiphy: Open-source, software defined radio modem | Hacker News
https://news.ycombinator.com/item?id=25814237
4 years ago by @bshanks
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hardware
sdr
wifi
fpgahardwaresdrwifi
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1Learning FPGAs [Book]
https://www.oreilly.com/library/view/learning-fpgas/9781491965481/
4 years ago by @bshanks
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1Precursor | Crowd Supply
https://www.crowdsupply.com/sutajio-kosagi/precursor
4 years ago by @bshanks
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1Introducing Precursor « bunnie's blog
https://www.bunniestudios.com/blog/?p=5921
4 years ago by @bshanks
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precursor
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1enjoy-digital/litex: Build your hardware, easily!
https://github.com/enjoy-digital/litex
4 years ago by @bshanks
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bunnie
fpga
migen
precursor
bunniefpgamigenprecursor
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1FPGA design for Software Engineers // Walk N' Squalk Coding Blog
https://www.walknsqualk.com/post/014-tiny-fpga-bx/
5 years ago by @bshanks
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ee
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1RISC-V CPU Gets A Peripheral | Hackaday
https://hackaday.com/2018/11/26/risc-v-cpu-gets-a-peripheral/
5 years ago by @bshanks
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1FINN-R: An End-to-End Deep-Learning Framework for Fast Exploration of Quantized Neural Networks
https://arxiv.org/pdf/1809.04570.pdf
6 years ago by @loroch
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deep_learning
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11809.01536.pdf
https://arxiv.org/pdf/1809.01536.pdf
6 years ago by @loroch
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1UPDuino: a $9.99 FPGA
https://tinyletter.com/jamesbowman/letters/upduino-a-9-99-fpga
6 years ago by @bshanks
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fpga
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1Cloud-Scale-Acceleration-Architecture.pdf
https://www.microsoft.com/en-us/research/wp-content/uploads/2016/10/Cloud-Scale-Acceleration-Architecture.pdf
6 years ago by @loroch
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distributed
fpga
distributedfpga
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1A Reconfigurable Fabric for Accelerating Large-Scale Datacenter Services
https://www.microsoft.com/en-us/research/publication/a-reconfigurable-fabric-for-accelerating-large-scale-datacenter-services/
6 years ago by @loroch
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2Scalable MatMul-free Language Modeling
R. Zhu, Y. Zhang, E. Sifferman, T. Sheaves, Y. Wang, D. Richmond, P. Zhou, and J. Eshraghian. (2024)
9 days ago by @taein.kim
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FPGA
LLM
FPGALLM
(0)
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1ZuSE KI-AVF
G. Thieu, S. Gesper, G. Payá-Vayá, C. Riggers, O. Renke, T. Fiedler, J. Marten, T. Stuckenberg, H. Blume, C. Weis and 18 other author(s). (2023)
6 months ago by @fabcho
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AI
ASIC
FPGA
RISC-V
acceleration
hardware-software
myown
processing
processor
sensor
system
vector
vertical
AIASICFPGARISC-Vaccelerationhardware-softwaremyownprocessingprocessorsensorsystemvectorvertical
(0)
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1Implementation of PID Controller PWM Module on FPGA
C. Thenmozhi. (October 2023)
7 months ago by @ijtsrd
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(PSO),
FPGA
Optimization
PID
Particle
Swarm
VLSI,
adjusting
controller,
delay,
error,
gain,
intelligenttechnology
laboratory
lag,
overshoot,
plant,
rise
system
time,
(PSO),FPGAOptimizationPIDParticleSwarmVLSI,adjustingcontroller,delay,error,gain,intelligenttechnologylaboratorylag,overshoot,plant,risesystemtime,
(0)
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1An Efficient Hardware Implementation of Canny Edge Detection Algorithm
K. Raja. (October 2023)
7 months ago by @ijtsrd
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FPGA
Virtex-5
Xilinx
algorithm,
approximation
canny
complexity,
computational
costs,
detection
detection,
dge
edge
hardware
latency,
methods,
pipelining
real-time
systems,
techniques,
FPGAVirtex-5Xilinxalgorithm,approximationcannycomplexity,computationalcosts,detectiondetection,dgeedgehardwarelatency,methods,pipeliningreal-timesystems,techniques,
(0)
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1Accelerating Attention Mechanism on FPGAs based on efficient Reconfigurable Systolic Array
wenhua ye. (2023)
a year ago by @csl_uth
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FPGA
ML
FPGAML
(0)
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1Feature Pyramid Networks for Object Detection
T. Lin, P. Dollár, R. Girshick, K. He, B. Hariharan, and S. Belongie. CoRR, (2016)
a year ago by @csl_uth
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FPGA
ML
FPGAML
(0)
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2FILM-QNN: Efficient FPGA Acceleration of Deep Neural Networks with Intra-Layer, Mixed-Precision Quantization
M. Sun, Z. Li, A. Lu, Y. Li, S. Chang, X. Ma, X. Lin, and Z. Fang. FPGA '22: The 2022 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Virtual Event, USA, 27 February 2022 - 1 March 2022, page 134--145. ACM, (2022)
a year ago by @csl_uth
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FPGA
ML
Quantization
FPGAMLQuantization
(0)
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2HAQ: Hardware-Aware Automated Quantization With Mixed Precision.
K. Wang, Z. Liu, Y. Lin, J. Lin, and S. Han. CVPR, page 8612-8620. Computer Vision Foundation / IEEE, (2019)
a year ago by @csl_uth
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FPGA
ML
Quantization
FPGAMLQuantization
(0)
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1MobileSP: An FPGA-Based Real-Time Keypoint Extraction Hardware Accelerator for Mobile VSLAM
Y. Liu, J. Li, K. Huang, X. Li, X. Qi, L. Chang, Y. Long, and J. Zhou. IEEE Trans. Circuits Syst. I Regul. Pap., 69 (12): 4919--4929 (2022)
a year ago by @csl_uth
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FPGA
ML
SLAM
FPGAMLSLAM
(0)
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3FROM FPGA TO ASIC IMPLEMENTATION OF AN OPENRISC BASED SOC FOR VOIP APPLICATION
F. Abid, and N. Izeboudjen. Informatics Engineering,an International Journal (IEIJ), 4 (1): 1 - 9 (March 2016)
2 years ago by @ieij1
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ASIC
FPGA
OpenRISC
Opencores
SoC
VoIP
ASICFPGAOpenRISCOpencoresSoCVoIP
(0)
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2FLOWER: A comprehensive dataflow compiler for high-level synthesis
P. Amiri, A. Pérard-Gayot, R. Membarth, P. Slusallek, R. Leißa, and S. Hack. (2021)cite arxiv:2112.07789.
3 years ago by @pooya_ww
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Compiler
Dataflow
FPGA
HLS
CompilerDataflowFPGAHLS
(0)
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1FPGA Based Design & Implementation of Alamouti MIMO Encoder for Wireless Transmitter
P. Raut, and S. Badjate. International Journal of Innovative Science and Modern Engineering (IJISME), 1 (9): 13-16 (August 2013)
3 years ago by @ijisme_beiesp
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(SNR)
Decoder
Encoder
FPGA
MIMO
Noise
OFDM
Ratio
Receiver
Signal
Transmitter
antenna
to
(SNR)DecoderEncoderFPGAMIMONoiseOFDMRatioReceiverSignalTransmitterantennato
(1)
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1A 2x2 FPGA based WRAP Tested for Colored Image Transmission in MIMO Systems
S. Kaushal, and S. Sharma. International Journal of Innovative Science and Modern Engineering (IJISME), 1 (6): 66-70 (May 2013)
3 years ago by @ijisme_beiesp
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(BER)
(MIMO)
(PSNR)
(STBC).
Bit
FPGA
Joint
Multiple
Peak
Space
WRAP
block
board
channel
coding
error
input
multiple
noise
output
rate
ratio
signal
source
time
to
(BER)(MIMO)(PSNR)(STBC).BitFPGAJointMultiplePeakSpaceWRAPblockboardchannelcodingerrorinputmultiplenoiseoutputrateratiosignalsourcetimeto
(1)
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1SONET/SDH: Review of Technology and Developments
D. Dhadwal, A. Arora, and V. Singh. International Journal of Innovative Science and Modern Engineering (IJISME), 2 (7): 1-6 (June 2014)
3 years ago by @ijisme_beiesp
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ARM
FPGA
Optical
SONET
SONET.
SONET/SDH
STS
carrier
for
ARMFPGAOpticalSONETSONET.SONET/SDHSTScarrierfor
(1)
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2Unexpected Diversity: Quantitative Memory Analysis for Zynq UltraScale+ Systems
K. Manev, A. Vaishnav, and D. Koch. 2019 International Conference on Field-Programmable Technology (ICFPT), page 179-187. (2019)
3 years ago by @csl_uth
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FPGA
FPGA
(0)
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1A Survey of FPGA-Based Robotic Computing.
Z. Wan, B. Yu, T. Li, J. Tang, Y. Zhu, Y. Wang, A. Raychowdhury, and S. Liu. CoRR, (2020)
3 years ago by @csl_uth
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FPGA
SLAM
FPGASLAM
(0)
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2A CAD-based methodology to optimize HLS code via the Roofline model
M. Siracusa, M. Rabozzi, E. Sozzo, L. Tucci, S. Williams, and M. Santambrogio. IEEE/ACM International Conference On Computer Aided Design, ICCAD 2020, San Diego, CA, USA, November 2-5, 2020, page 116:1--116:9. IEEE, (2020)
3 years ago by @csl_uth
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FPGA
Roofline
FPGARoofline
(0)
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1Embedded Implementations of Real Time Video Stabilization Mechanisms A Comprehensive Review
M. Singh. International Journal of Trend in Scientific Research and Development, 5 (3): 685-693 (April 2021)
3 years ago by @ijtsrd
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Estimation
FPGA
Motion
Real-time
SIFT
SURF
Stabilization
EstimationFPGAMotionReal-timeSIFTSURFStabilization
(0)
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1Proposal of ROS-compliant FPGA Component for Low-Power Robotic Systems.
K. Yamashina, T. Ohkawa, K. Ootsu, and T. Yokota. CoRR, (2015)
4 years ago by @csl_uth
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FPGA
ROS
SLAM
FPGAROSSLAM
(0)
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2A Methodology for Principled Approximation in Visual SLAM.
Y. Pei, S. Biswas, D. Fussell, and K. Pingali. PACT, page 373-386. ACM, (2020)
4 years ago by @csl_uth
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FPGA
SLAM
FPGASLAM
(0)
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