%0 Conference Paper
%1 SheQia18Towards
%A Shen, Junzhong
%A Qiao, Yuran
%A Huang, You
%A Wen, Mei
%A Zhang, Chunyuan
%B Circuits and Systems (ISCAS), 2018 IEEE International Symposium on
%D 2018
%K FPGA architecture hardware matrix_vector_mult
%P 1--5
%T Towards a multi-array architecture for accelerating large-scale matrix multiplication on FPGAs
%U https://arxiv.org/pdf/1803.03790.pdf
@inproceedings{SheQia18Towards,
added-at = {2018-08-22T09:55:39.000+0200},
author = {Shen, Junzhong and Qiao, Yuran and Huang, You and Wen, Mei and Zhang, Chunyuan},
biburl = {https://www.bibsonomy.org/bibtex/2fae685bafdc06774893d8c2a3be27b56/loroch},
booktitle = {Circuits and Systems (ISCAS), 2018 IEEE International Symposium on},
interhash = {075811f89adb30ac48f0ac82536c523f},
intrahash = {fae685bafdc06774893d8c2a3be27b56},
keywords = {FPGA architecture hardware matrix_vector_mult},
organization = {IEEE},
pages = {1--5},
timestamp = {2018-08-22T09:55:39.000+0200},
title = {Towards a multi-array architecture for accelerating large-scale matrix multiplication on FPGAs},
url = {https://arxiv.org/pdf/1803.03790.pdf},
year = 2018
}