%0 Journal Article %1 journals/tecs/CoussyCBBM06 %A Coussy, Philippe %A Casseau, Emmanuel %A Bomel, Pierre %A Baganne, Adel %A Martin, Eric %D 2006 %J ACM Trans. Embed. Comput. Syst. %K dblp %N 1 %P 29-53 %T A formal method for hardware IP design and integration under I/O and timing constraints. %U http://dblp.uni-trier.de/db/journals/tecs/tecs5.html#CoussyCBBM06 %V 5

@article{journals/tecs/CoussyCBBM06, added-at = {2020-09-08T00:00:00.000+0200}, author = {Coussy, Philippe and Casseau, Emmanuel and Bomel, Pierre and Baganne, Adel and Martin, Eric}, biburl = {https://www.bibsonomy.org/bibtex/28ba77ecee956c0764a0fa041fc778368/dblp}, ee = {https://doi.org/10.1145/1132357.1132359}, interhash = {64b7101f6145cf018d9f590cbd586dc1}, intrahash = {8ba77ecee956c0764a0fa041fc778368}, journal = {ACM Trans. Embed. Comput. Syst.}, keywords = {dblp}, number = 1, pages = {29-53}, timestamp = {2020-09-09T12:40:48.000+0200}, title = {A formal method for hardware IP design and integration under I/O and timing constraints.}, url = {http://dblp.uni-trier.de/db/journals/tecs/tecs5.html#CoussyCBBM06}, volume = 5, year = 2006 }