%0 Journal Article %1 journals/tcad/YuZLCH17 %A Yu, Cunxi %A Zhang, Xiangyu %A Liu, Duo %A Ciesielski, Maciej J. %A Holcomb, Daniel E. %D 2017 %J IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. %K dblp %N 10 %P 1647-1659 %T Incremental SAT-Based Reverse Engineering of Camouflaged Logic Circuits. %U http://dblp.uni-trier.de/db/journals/tcad/tcad36.html#YuZLCH17 %V 36

@article{journals/tcad/YuZLCH17, added-at = {2022-10-02T00:00:00.000+0200}, author = {Yu, Cunxi and Zhang, Xiangyu and Liu, Duo and Ciesielski, Maciej J. and Holcomb, Daniel E.}, biburl = {https://www.bibsonomy.org/bibtex/25a3ea7c5eab55fbc2a3ce0a1d2bdac1a/dblp}, ee = {https://doi.org/10.1109/TCAD.2017.2652220}, interhash = {7b449e074b809d843443f0336616d03c}, intrahash = {5a3ea7c5eab55fbc2a3ce0a1d2bdac1a}, journal = {IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.}, keywords = {dblp}, number = 10, pages = {1647-1659}, timestamp = {2024-04-08T19:47:19.000+0200}, title = {Incremental SAT-Based Reverse Engineering of Camouflaged Logic Circuits.}, url = {http://dblp.uni-trier.de/db/journals/tcad/tcad36.html#YuZLCH17}, volume = 36, year = 2017 }