%0 Journal Article %1 journals/ijpp/OttavianoBBVCRBB24 %A Ottaviano, Alessandro %A Balas, Robert %A Bambini, Giovanni %A del Vecchio, Antonio %A Ciani, Maicol %A Rossi, Davide %A Benini, Luca %A Bartolini, Andrea %D 2024 %J Int. J. Parallel Program. %K dblp %N 1-2 %P 93-123 %T ControlPULP: A RISC-V On-Chip Parallel Power Controller for Many-Core HPC Processors with FPGA-Based Hardware-In-The-Loop Power and Thermal Emulation. %U http://dblp.uni-trier.de/db/journals/ijpp/ijpp52.html#OttavianoBBVCRBB24 %V 52

@article{journals/ijpp/OttavianoBBVCRBB24, added-at = {2024-10-06T00:00:00.000+0200}, author = {Ottaviano, Alessandro and Balas, Robert and Bambini, Giovanni and del Vecchio, Antonio and Ciani, Maicol and Rossi, Davide and Benini, Luca and Bartolini, Andrea}, biburl = {https://www.bibsonomy.org/bibtex/2ee80852ee2be3c4c70bb9dfa60bfe95d/dblp}, ee = {https://doi.org/10.1007/s10766-024-00761-4}, interhash = {88f2db21206eaf00b4ee024bb7765517}, intrahash = {ee80852ee2be3c4c70bb9dfa60bfe95d}, journal = {Int. J. Parallel Program.}, keywords = {dblp}, month = {April}, number = {1-2}, pages = {93-123}, timestamp = {2024-10-07T07:07:02.000+0200}, title = {ControlPULP: A RISC-V On-Chip Parallel Power Controller for Many-Core HPC Processors with FPGA-Based Hardware-In-The-Loop Power and Thermal Emulation.}, url = {http://dblp.uni-trier.de/db/journals/ijpp/ijpp52.html#OttavianoBBVCRBB24}, volume = 52, year = 2024 }