%0 Journal Article %1 Turner:2004:HEL:1044385.1044397 %A Turner, R. H. %A Woods, R. F. %C Piscataway, NJ, USA %D 2004 %I IEEE Educational Activities Department %J IEEE Trans. Very Large Scale Integr. Syst. %K FPGA architecture multiplier %N 10 %P 1113--1117 %R 10.1109/TVLSI.2004.833399 %T Highly Efficient, Limited Range Multipliers for LUT-based FPGA Architectures %U https://doi.org/10.1109/TVLSI.2004.833399 %V 12 %X A novel design technique for deriving highly efficient multipliers that operate on a limited range of multiplier values is presented. Using the technique, Xilinx Virtex field programmable gate array (FPGA) implementations for a discrete cosine transform and poly-phase filter were derived with area reductions of 31%-70% and speed increases of 5%-35% when compared to designs using general-purpose multipliers. The technique gives superior results over other fixed coefficient methods and is applicable to a range of FPGA technologies.

@article{Turner:2004:HEL:1044385.1044397, abstract = {A novel design technique for deriving highly efficient multipliers that operate on a limited range of multiplier values is presented. Using the technique, Xilinx Virtex field programmable gate array (FPGA) implementations for a discrete cosine transform and poly-phase filter were derived with area reductions of 31%-70% and speed increases of 5%-35% when compared to designs using general-purpose multipliers. The technique gives superior results over other fixed coefficient methods and is applicable to a range of FPGA technologies.}, acmid = {1044397}, added-at = {2018-06-12T16:16:33.000+0200}, address = {Piscataway, NJ, USA}, author = {Turner, R. H. and Woods, R. F.}, biburl = {https://www.bibsonomy.org/bibtex/261d5fe5fbfff8d3f3e8fcb27dc29b5d9/loroch}, description = {Highly efficient, limited range multipliers for LUT-based FPGA architectures}, doi = {10.1109/TVLSI.2004.833399}, interhash = {8a51b6e2011bbfd469fdc2feace86368}, intrahash = {61d5fe5fbfff8d3f3e8fcb27dc29b5d9}, issn = {1063-8210}, issue_date = {October 2004}, journal = {IEEE Trans. Very Large Scale Integr. Syst.}, keywords = {FPGA architecture multiplier}, month = oct, number = 10, numpages = {5}, pages = {1113--1117}, publisher = {IEEE Educational Activities Department}, timestamp = {2018-06-12T16:16:33.000+0200}, title = {Highly Efficient, Limited Range Multipliers for LUT-based FPGA Architectures}, url = {https://doi.org/10.1109/TVLSI.2004.833399}, volume = 12, year = 2004 }