%0 Conference Paper %1 conf/aspdac/GuoCZH07 %A Guo, Liangpeng %A Cai, Yici %A Zhou, Qiang %A Hong, Xianlong %B ASP-DAC %D 2007 %I IEEE Computer Society %K dblp %P 666-671 %T Logic and Layout Aware Voltage Island Generation for Low Power Design. %U http://dblp.uni-trier.de/db/conf/aspdac/aspdac2007.html#GuoCZH07 %@ 1-4244-0629-3

@inproceedings{conf/aspdac/GuoCZH07, added-at = {2023-03-23T00:00:00.000+0100}, author = {Guo, Liangpeng and Cai, Yici and Zhou, Qiang and Hong, Xianlong}, biburl = {https://www.bibsonomy.org/bibtex/2724ea745d61929861eac9d49b633ee29/dblp}, booktitle = {ASP-DAC}, crossref = {conf/aspdac/2007}, ee = {http://dl.acm.org/citation.cfm?id=1323483}, interhash = {8e1fca7d0f4e368534e0bb4a91a5f7ce}, intrahash = {724ea745d61929861eac9d49b633ee29}, isbn = {1-4244-0629-3}, keywords = {dblp}, pages = {666-671}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T04:16:52.000+0200}, title = {Logic and Layout Aware Voltage Island Generation for Low Power Design.}, url = {http://dblp.uni-trier.de/db/conf/aspdac/aspdac2007.html#GuoCZH07}, year = 2007 }