%0 Journal Article %1 journals/ieicet/MasuiMTT05 %A Masui, Shoichi %A Mukaida, Kenji %A Takenaka, Masahiko %A Torii, Naoya %D 2005 %J IEICE Trans. Electron. %K dblp %N 4 %P 576-581 %T Design Optimization of a High-Speed, Area-Efficient and Low-Power Montgomery Modular Multiplier for RSA Algorithm. %U http://dblp.uni-trier.de/db/journals/ieicet/ieicet88c.html#MasuiMTT05 %V 88-C

@article{journals/ieicet/MasuiMTT05, added-at = {2020-04-11T00:00:00.000+0200}, author = {Masui, Shoichi and Mukaida, Kenji and Takenaka, Masahiko and Torii, Naoya}, biburl = {https://www.bibsonomy.org/bibtex/200e5aa99c0f3dce67af2a37011f77ba4/dblp}, ee = {https://doi.org/10.1093/ietele/e88-c.4.576}, interhash = {c182cf9036a4220c3e1c91e028e1c48e}, intrahash = {00e5aa99c0f3dce67af2a37011f77ba4}, journal = {IEICE Trans. Electron.}, keywords = {dblp}, number = 4, pages = {576-581}, timestamp = {2020-04-14T11:42:16.000+0200}, title = {Design Optimization of a High-Speed, Area-Efficient and Low-Power Montgomery Modular Multiplier for RSA Algorithm.}, url = {http://dblp.uni-trier.de/db/journals/ieicet/ieicet88c.html#MasuiMTT05}, volume = {88-C}, year = 2005 }