%0 Journal Article %1 journals/ipsj/TakataM09 %A Takata, Taiga %A Matsunaga, Yusuke %D 2009 %J IPSJ Trans. Syst. LSI Des. Methodol. %K dblp %P 200-211 %T Area Recovery under Depth Constraint for Technology Mapping for LUT-based FPGAs. %U http://dblp.uni-trier.de/db/journals/ipsj/ipsj2.html#TakataM09 %V 2

@article{journals/ipsj/TakataM09, added-at = {2020-09-29T00:00:00.000+0200}, author = {Takata, Taiga and Matsunaga, Yusuke}, biburl = {https://www.bibsonomy.org/bibtex/2a666378f1b1f9ea0c7a3e75d73022a14/dblp}, ee = {https://doi.org/10.2197/ipsjtsldm.2.200}, interhash = {c1c38b83449fe36aa30cac3dbee8c277}, intrahash = {a666378f1b1f9ea0c7a3e75d73022a14}, journal = {IPSJ Trans. Syst. LSI Des. Methodol.}, keywords = {dblp}, pages = {200-211}, timestamp = {2020-09-30T11:34:25.000+0200}, title = {Area Recovery under Depth Constraint for Technology Mapping for LUT-based FPGAs.}, url = {http://dblp.uni-trier.de/db/journals/ipsj/ipsj2.html#TakataM09}, volume = 2, year = 2009 }