%0 Conference Paper %1 conf/vlsic/MathewSSAKAHCKD16 %A Mathew, Sanu %A Satpathy, Sudhir %A Suresh, Vikram B. %A Anders, Mark A. %A Kaul, Himanshu %A Agarwal, Amit %A Hsu, Steven %A Chen, Gregory K. %A Krishnamurthy, Ram %A De, Vivek %B VLSI Circuits %D 2016 %I IEEE %K dblp %P 1-2 %T A 4fJ/bit delay-hardened physically unclonable function circuit with selective bit destabilization in 14nm tri-gate CMOS. %U http://dblp.uni-trier.de/db/conf/vlsic/vlsic2016.html#MathewSSAKAHCKD16 %@ 978-1-5090-0635-9

@inproceedings{conf/vlsic/MathewSSAKAHCKD16, added-at = {2022-02-25T00:00:00.000+0100}, author = {Mathew, Sanu and Satpathy, Sudhir and Suresh, Vikram B. and Anders, Mark A. and Kaul, Himanshu and Agarwal, Amit and Hsu, Steven and Chen, Gregory K. and Krishnamurthy, Ram and De, Vivek}, biburl = {https://www.bibsonomy.org/bibtex/27ead29cf48cd84604a247f9e0eb0b006/dblp}, booktitle = {VLSI Circuits}, crossref = {conf/vlsic/2016}, ee = {https://doi.org/10.1109/VLSIC.2016.7573554}, interhash = {ccdd8587f41e9feaddcbf3a1efbd5138}, intrahash = {7ead29cf48cd84604a247f9e0eb0b006}, isbn = {978-1-5090-0635-9}, keywords = {dblp}, pages = {1-2}, publisher = {IEEE}, timestamp = {2024-04-10T15:34:06.000+0200}, title = {A 4fJ/bit delay-hardened physically unclonable function circuit with selective bit destabilization in 14nm tri-gate CMOS.}, url = {http://dblp.uni-trier.de/db/conf/vlsic/vlsic2016.html#MathewSSAKAHCKD16}, year = 2016 }