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A 4fJ/bit delay-hardened physically unclonable function circuit with selective bit destabilization in 14nm tri-gate CMOS.

, , , , , , , , , и . VLSI Circuits, стр. 1-2. IEEE, (2016)

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Mahalakshmi Krishnamurthy

Adarsh Krishnamurthy

Arvind Krishnamurthy

Johann Ram

Ram Gopal

 

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