%0 Journal Article %1 journals/tcasII/XiaoQCSLWW24 %A Xiao, Kanglin %A Qiao, Xin %A Cui, Xiaoxin %A Song, Jiahao %A Luo, Haoyang %A Wang, Xin'an %A Wang, Yuan %D 2024 %J IEEE Trans. Circuits Syst. II Express Briefs %K dblp %N 7 %P 3263-3267 %T A 28nm 8Kb Reconfigurable SRAM Computing-In-Memory Macro With Input-Sparsity Optimized DTC for Multi-Mode MAC Operations. %U http://dblp.uni-trier.de/db/journals/tcasII/tcasII71.html#XiaoQCSLWW24 %V 71

@article{journals/tcasII/XiaoQCSLWW24, added-at = {2024-07-19T00:00:00.000+0200}, author = {Xiao, Kanglin and Qiao, Xin and Cui, Xiaoxin and Song, Jiahao and Luo, Haoyang and Wang, Xin'an and Wang, Yuan}, biburl = {https://www.bibsonomy.org/bibtex/2fff84ee2f7268e36e1c3a822c9d23388/dblp}, ee = {https://doi.org/10.1109/TCSII.2024.3360284}, interhash = {d7cc5da30218a9f417e9f75bffc77e5e}, intrahash = {fff84ee2f7268e36e1c3a822c9d23388}, journal = {IEEE Trans. Circuits Syst. II Express Briefs}, keywords = {dblp}, month = {July}, number = 7, pages = {3263-3267}, timestamp = {2024-07-22T07:06:54.000+0200}, title = {A 28nm 8Kb Reconfigurable SRAM Computing-In-Memory Macro With Input-Sparsity Optimized DTC for Multi-Mode MAC Operations.}, url = {http://dblp.uni-trier.de/db/journals/tcasII/tcasII71.html#XiaoQCSLWW24}, volume = 71, year = 2024 }