%0 Journal Article %1 journals/ijcta/LopezHBC09 %A López, Paula %A Hauer, Johann %A Blanco-Filgueira, Beatriz %A Cabello, Diego %D 2009 %J Int. J. Circuit Theory Appl. %K dblp %N 2 %P 163-177 %T A dc I-V model for short-channel polygonal enclosed-layout transistors. %U http://dblp.uni-trier.de/db/journals/ijcta/ijcta37.html#LopezHBC09 %V 37

@article{journals/ijcta/LopezHBC09, added-at = {2023-01-31T00:00:00.000+0100}, author = {López, Paula and Hauer, Johann and Blanco-Filgueira, Beatriz and Cabello, Diego}, biburl = {https://www.bibsonomy.org/bibtex/2d31ac3b60121add048c4a1ee5eb527e7/dblp}, ee = {https://doi.org/10.1002/cta.537}, interhash = {e2502760a9f88bcf28989d10674277de}, intrahash = {d31ac3b60121add048c4a1ee5eb527e7}, journal = {Int. J. Circuit Theory Appl.}, keywords = {dblp}, number = 2, pages = {163-177}, timestamp = {2024-04-08T20:20:53.000+0200}, title = {A dc I-V model for short-channel polygonal enclosed-layout transistors.}, url = {http://dblp.uni-trier.de/db/journals/ijcta/ijcta37.html#LopezHBC09}, volume = 37, year = 2009 }