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A dc I-V model for short-channel polygonal enclosed-layout transistors.

, , , and . Int. J. Circuit Theory Appl., 37 (2): 163-177 (2009)

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An analog CMOS realisation of a reconfigurable discrete-time cellular neural network., , and . ICECS, page 285-288. IEEE, (1998)A General-Purpose CMOS Vision Sensor with In-Pixel 5-bit Convolutional Layer Computation., , , , and . ICECS 2022, page 1-4. IEEE, (2022)An 11 mA Capacitor-Less LDO With 3.08 nA Quiescent Current and SSF-Based Adaptive Biasing., , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 69 (3): 844-848 (2022)A CMOS Vision Sensor for Background Subtraction., , , and . ISCAS, page 1-5. IEEE, (2020)Design methodology of a 0.7 V, 64.5 pW @ 36°C, 1830μm2 Subthreshold Voltage Reference for Implantable Devices., , , , and . ICECS, page 386-389. IEEE, (2019)Voltage boosters for on-chip solar cells on focal-plane processors., , , , , and . ICECS, page 393-396. IEEE, (2013)CNN Implementation of Spin Filters for Electronic Speckle Pattern Interferometry Applications., , , and . ISCAS, page 2674-2677. IEEE, (2007)Live demonstration: Wireless sensor network for snail pest detection., , , , , , and . ISCAS, page 2371. IEEE, (2016)Simplification and hardware implementation of the feature descriptor vector calculation in the SIFT algorithm., , , , , , and . FPL, page 1-4. IEEE, (2014)Optimization Neural Networks for Image Segmentation., , and . IWANN, volume 930 of Lecture Notes in Computer Science, page 860-867. Springer, (1995)