%0 Conference Paper %1 conf/isca/ChenXLSGLLHLCLP20 %A Chen, Chen %A Xiang, Xiaoyan %A Liu, Chang %A Shang, Yunhai %A Guo, Ren %A Liu, Dongqi %A Lu, Yimin %A Hao, Ziyi %A Luo, Jiahui %A Chen, Zhijian %A Li, Chunqiang %A Pu, Yu %A Meng, Jianyi %A Yan, Xiaolang %A Xie, Yuan %A Qi, Xiaoning %B ISCA %D 2020 %I IEEE %K dblp %P 52-64 %T Xuantie-910: A Commercial Multi-Core 12-Stage Pipeline Out-of-Order 64-bit High Performance RISC-V Processor with Vector Extension : Industrial Product. %U http://dblp.uni-trier.de/db/conf/isca/isca2020.html#ChenXLSGLLHLCLP20 %@ 978-1-7281-4661-4

@inproceedings{conf/isca/ChenXLSGLLHLCLP20, added-at = {2024-10-06T00:00:00.000+0200}, author = {Chen, Chen and Xiang, Xiaoyan and Liu, Chang and Shang, Yunhai and Guo, Ren and Liu, Dongqi and Lu, Yimin and Hao, Ziyi and Luo, Jiahui and Chen, Zhijian and Li, Chunqiang and Pu, Yu and Meng, Jianyi and Yan, Xiaolang and Xie, Yuan and Qi, Xiaoning}, biburl = {https://www.bibsonomy.org/bibtex/25b2d51a4ebf274aba977dbb7b167ae76/dblp}, booktitle = {ISCA}, crossref = {conf/isca/2020}, ee = {https://doi.org/10.1109/ISCA45697.2020.00016}, interhash = {e533bb69eff959e98e75c5703355ef7c}, intrahash = {5b2d51a4ebf274aba977dbb7b167ae76}, isbn = {978-1-7281-4661-4}, keywords = {dblp}, pages = {52-64}, publisher = {IEEE}, timestamp = {2024-10-07T09:01:09.000+0200}, title = {Xuantie-910: A Commercial Multi-Core 12-Stage Pipeline Out-of-Order 64-bit High Performance RISC-V Processor with Vector Extension : Industrial Product.}, url = {http://dblp.uni-trier.de/db/conf/isca/isca2020.html#ChenXLSGLLHLCLP20}, year = 2020 }