%0 Conference Paper %1 conf/asap/WangL0ZHK19 %A Wang, Feng %A Luo, Guojie %A Sun, Guangyu %A Zhang, Jiaxi %A Huang, Peng %A Kang, Jinfeng %B ASAP %D 2019 %I IEEE %K dblp %P 157-164 %T Parallel Stateful Logic in RRAM: Theoretical Analysis and Arithmetic Design. %U http://dblp.uni-trier.de/db/conf/asap/asap2019.html#WangL0ZHK19 %@ 978-1-7281-1601-3

@inproceedings{conf/asap/WangL0ZHK19, added-at = {2022-11-08T00:00:00.000+0100}, author = {Wang, Feng and Luo, Guojie and Sun, Guangyu and Zhang, Jiaxi and Huang, Peng and Kang, Jinfeng}, biburl = {https://www.bibsonomy.org/bibtex/245a165d1bc17bbddad1a17c70469e4a5/dblp}, booktitle = {ASAP}, crossref = {conf/asap/2019}, ee = {https://doi.org/10.1109/ASAP.2019.000-8}, interhash = {f654bbe9bac5845023da4391099afa9f}, intrahash = {45a165d1bc17bbddad1a17c70469e4a5}, isbn = {978-1-7281-1601-3}, keywords = {dblp}, pages = {157-164}, publisher = {IEEE}, timestamp = {2024-04-10T22:07:51.000+0200}, title = {Parallel Stateful Logic in RRAM: Theoretical Analysis and Arithmetic Design.}, url = {http://dblp.uni-trier.de/db/conf/asap/asap2019.html#WangL0ZHK19}, year = 2019 }