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Improving simulation speed and accuracy for many-core embedded platforms with ensemble models.

, , , , , , and . DATE, page 671-676. EDA Consortium San Jose, CA, USA / ACM DL, (2013)

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Low-power branch prediction techniques for VLIW architectures: a compiler-hints based approach., , , , , and . Integr., 38 (3): 515-524 (2005)AES Power Attack Based on Induced Cache Miss and Countermeasure., , , , and . ITCC (1), page 586-591. IEEE Computer Society, (2005)Yield enhancement by robust application-specific mapping on Network-on-Chips., , , and . NoCArc@MICRO, page 37-42. ACM, (2009)A meta-model assisted coprocessor synthesis framework for compiler/architecture parameters customization., , , and . DATE, page 659-664. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Variability-aware robust design space exploration of chip multiprocessor architectures., , and . ASP-DAC, page 323-328. IEEE, (2009)Improving simulation speed and accuracy for many-core embedded platforms with ensemble models., , , , , , and . DATE, page 671-676. EDA Consortium San Jose, CA, USA / ACM DL, (2013)OpenCL Application Auto-tuning and Run-Time Resource Management for Multi-core Platforms., , , , , , , , , and 1 other author(s). ISPA, page 127-133. IEEE Computer Society, (2014)A design space exploration methodology supporting run-time resource management for multi-processor Systems-on-chip., , , and . SASP, page 21-28. IEEE Computer Society, (2009)Power Exploration for Embedded VLIW Architectures., , , and . ICCAD, page 498-503. IEEE Computer Society, (2000)An Instruction-Level Methodology for Power Estimation and Optimization of Embedded VLIW Cores., , , , , and . DATE, page 1128. IEEE Computer Society, (2002)