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Disambiguation of "Pan, David Z."

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OpenMPL: An Open-Source Layout Decomposer.

, , , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 40 (11): 2331-2344 (2021)

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David Tse-chien Pan

Z Taufig

Petra Pan

Xiaoqing Pan

Weiqing Pan

 

Other publications of authors with the same name

Skew Bounded Buffer Tree Resynthesis For Clock Power Optimization., , , , , and . ACM Great Lakes Symposium on VLSI, page 87-90. ACM, (2015)Total power optimization combining placement, sizing and multi-Vt through slack distribution management., , and . ASP-DAC, page 352-357. IEEE, (2008)BOB-router: A new buffering-aware global router with over-the-block routing resources optimization., , and . ASP-DAC, page 513-518. IEEE, (2014)Self-aligned double patterning layout decomposition with complementary e-beam lithography., , and . ASP-DAC, page 143-148. IEEE, (2014)Machine learning and pattern matching in physical design., , , and . ASP-DAC, page 286-293. IEEE, (2015)A high-performance triple patterning layout decomposer with balanced density., , , , , and . ICCAD, page 163-169. IEEE, (2013)Methodology for Standard Cell Compliance and Detailed Placement for Triple Patterning Lithography., , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 34 (5): 726-739 (2015)A Bandwidth-Adaptive Pipelined SAR ADC With Three-Stage Cascoded Floating Inverter Amplifier., , , , , , and . IEEE J. Solid State Circuits, 58 (9): 2564-2574 (September 2023)Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization., , , , , , , , , and 31 other author(s). CoRR, (2020)Machine learning for IC design and technology co-optimization in extreme scaling.. VLSI-DAT, page 1. IEEE, (2018)