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Symbolic Execution based Verification of Compliance with the ISO 26262 Functional Safety Standard., and . DTIS, page 1-6. IEEE, (2019)A Novel Architecture of CXL Protocol Data Link Layer for Low Latency Memory Access., , , , , and . ICM, page 298-303. IEEE, (2023)Optimized FPGA Architecture for Machine Learning Applications using Posit Multipliers., , and . ICM, page 50-53. IEEE, (2022)Hardware-accelerated SOME/IP-based Serialization for AUTOSAR Platforms., , and . DTIS, page 1-2. IEEE, (2020)Solving constraints in FPGA detailed routing using SMT., and . ICECS, page 613-616. IEEE, (2015)Toward the interfacing of systemC-AMS models with hardware-emulated platforms., , , , and . IDT, page 54-59. IEEE, (2015)Ultra-Fast DMAC TLM Model for High Speed Virtual Platform Simulation., , and . MTV, page 39-44. IEEE Computer Society, (2013)FPGA Based Accelerator for 3-SAT Conflict Analysis in SAT Solvers., , and . CHARME, volume 3725 of Lecture Notes in Computer Science, page 384-387. Springer, (2005)SystemVerilog assertion debugging: A visualization and pattern matching model., , , and . PACRIM, page 385-390. IEEE, (2015)Verification of Neural Networks for Safety Critical Applications., , and . ICM, page 1-4. IEEE, (2020)