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17.3 A -58dBc-Worst-Fractional-Spur and -234dB-FoMjitter, 5.5GHz Ring-DCO-Based Fractional-N DPLL Using a Time-Invariant-Probability Modulator, Generating a Nonlinearity-Robust DTC-Control Word.

T. Seong, Y. Lee, C. Hwang, J. Lee, H. Park, K. Lee, and J. Choi. ISSCC, page 270-272. IEEE, (2020)

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Chanwoong Park

Hak Hwang

Sungil Hwang

Byung Kook Hwang

Kyung-Yub Hwang

Other publications of authors with the same name

A 365fsrms-Jitter and -63dBc-Fractional Spur 5.3GHz-Ring-DCO-Based Fractional-N DPLL Using a DTC Second/Third- Order Nonlinearity Cancelation and a Probability-Density-Shaping Δ ΣM.H. Park, C. Hwang, T. Seong, Y. Lee, and J. Choi. ISSCC, page 442-444. IEEE, (2021)Research on Improvement of Anomaly Detection Performance in Industrial Control Systems.S. Bae, C. Hwang, and T. Lee. WISA, volume 13009 of Lecture Notes in Computer Science, page 76-87. Springer, (2021)A 188fsrms-Jitter and -243d8-FoMjitter 5.2GHz-Ring-DCO-Based Fractional-N Digital PLL with a 1/8 DTC-Range-Reduction Technique Using a Quadruple-Timing-Margin Phase Selector.C. Hwang, H. Park, T. Seong, and J. Choi. ISSCC, page 378-380. IEEE, (2022)17.3 A -58dBc-Worst-Fractional-Spur and -234dB-FoMjitter, 5.5GHz Ring-DCO-Based Fractional-N DPLL Using a Time-Invariant-Probability Modulator, Generating a Nonlinearity-Robust DTC-Control Word.T. Seong, Y. Lee, C. Hwang, J. Lee, H. Park, K. Lee, and J. Choi. ISSCC, page 270-272. IEEE, (2020)An 82fsrms-Jitter and 22.5mW-Power, 102GHz W-Band PLL Using a Power-Gating Injection-Locked Frequency-Multiplier- Based Phase Detector in 65nm CMOS.S. Yoo, S. Park, S. Choi, Y. Cho, H. Yoon, C. Hwang, and J. Choi. ISSCC, page 330-332. IEEE, (2021)A 135fsrms-Jitter 0.6-to-7.7GHz LO Generator Using a Single LC-VCO-Based Subsampling PLL and a Ring-Oscillator-Based Sub-Integer-N Frequency Multiplier.Y. Jo, J. Kim, Y. Shin, C. Hwang, H. Park, and J. Choi. ISSCC, page 76-77. IEEE, (2023)10.2 A 5.5μs-Calibration-Time, Low-Jitter, and Compact-Area Fractional-N Digital PLL Using the Recursive-Least-Squares (RLS) Algorithm.S. Jang, M. Chae, H. Park, C. Hwang, and J. Choi. ISSCC, page 190-192. IEEE, (2024)A Low-Jitter Ring-DCO-Based Fractional-N Digital PLL With a 1/8 DTC-Range-Reduction Technique Using a Quadruple-Timing-Margin Phase Selector.H. Park, C. Hwang, T. Seong, and J. Choi. IEEE J. Solid State Circuits, 57 (12): 3527-3537 (2022)17.1 A -240dB-FoMjitter and -115dBc/Hz PN @ 100kHz, 7.7GHz Ring-DCO-Based Digital PLL Using P/I-Gain Co-Optimization and Sequence-Rearranged Optimally Spaced TDC for Flicker-Noise Reduction.Y. Lee, T. Seong, J. Lee, C. Hwang, H. Park, and J. Choi. ISSCC, page 266-268. IEEE, (2020)

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Disambiguation of "Hwang, Chanwoong"