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Disambiguation of "Sacchetto, Davide"

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Vertically-stacked double-gate nanowire FETs with controllable polarity: from devices to regular ASICs.

, , , , , , and . DATE, page 625-630. EDA Consortium San Jose, CA, USA / ACM DL, (2013)

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Davide Cadamuro

Davide Pennino

Davide Batic

Davide Pagani

Davide Cantoni

 

Other publications of authors with the same name

Co-Design of ReRAM Passive Crossbar Arrays Integrated in 180 nm CMOS Technology., , , , , , , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 6 (3): 339-351 (2016)Multiterminal Memristive Nanowire Devices for Logic and Memory Applications: A Review., , and . Proc. IEEE, 100 (6): 2008-2020 (2012)Alternative design methodologies for the next generation logic switch., , , and . ICCAD, page 231-234. IEEE Computer Society, (2011)Memristive devices fabricated with silicon nanowire schottky barrier transistors., , , , and . ISCAS, page 9-12. IEEE, (2010)Design aspects of carry lookahead adders with vertically-stacked nanowire transistors., , , and . ISCAS, page 1715-1718. IEEE, (2010)Vertically-stacked double-gate nanowire FETs with controllable polarity: from devices to regular ASICs., , , , , , and . DATE, page 625-630. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Low-voltage read/write circuit design for transistorless ReRAM crossbar arrays in 180nm CMOS technology., , , , and . ISCAS, page 9-12. IEEE, (2015)GMS: Generic memristive structure for non-volatile FPGAs., , , , and . VLSI-SoC, page 94-98. IEEE, (2012)Process/design co-optimization of regular logic tiles for double-gate silicon nanowire transistors., , , , , , and . NANOARCH, page 55-60. ACM, (2012)Towards structured ASICs using polarity-tunable Si nanowire transistors., , , , , , and . DAC, page 123:1-123:4. ACM, (2013)