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Multiobjective VLSI cell placement using distributed simulated evolution algorithm.

, , and . ISCAS (6), page 6226-6229. IEEE, (2005)

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Exposing ILP in custom hardware with a dataflow compiler IR.. PACT, page 411. IEEE Computer Society, (2013)Evaluating Parallel Simulated Evolution Strategies for VLSI Cell Placement., , and . J. Math. Model. Algorithms, 6 (3): 433-454 (2007)Comparative evaluation of parallelization strategies for evolutionary and stochastic heuristics., , , and . GECCO, page 921-922. ACM, (2005)Value State Flow Graph: A Dataflow Compiler IR for Accelerating Control-Intensive Code in Spatial Hardware., and . ACM Trans. Reconfigurable Technol. Syst., 9 (2): 14:1-14:22 (2016)Multiobjective VLSI cell placement using distributed simulated evolution algorithm., , and . ISCAS (6), page 6226-6229. IEEE, (2005)Loopapalooza: Investigating Limits of Loop-Level Parallelism with a Compiler-Driven Approach., , , and . ISPASS, page 128-138. IEEE, (2021)Achieving Superscalar Performance without Superscalar Overheads - A Dataflow Compiler IR for Custom Computing., and . ICCSW, volume 35 of OASIcs, page 136-143. Schloss Dagstuhl - Leibniz-Zentrum fuer Informatik, Germany, (2013)Accelerating control-flow intensive code in spatial hardware.. University of Cambridge, UK, (2015)British Library, EThOS.Performance Analysis of DiffServ based Quality of Service in a Multimedia Wired Network and VPN effect using OPNET, , and . CoRR, (2012)A New Dataflow Compiler IR for Accelerating Control-Intensive Code in Spatial Hardware., and . IPDPS Workshops, page 122-131. IEEE Computer Society, (2014)