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Design for Secure Test - A Case Study on Pipelined Advanced Encryption Standard.

, , , and . ISCAS, page 149-152. IEEE, (2007)

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A floorplan-driven high-level synthesis algorithm with operation chainings using chaining enumeration., , and . APCCAS, page 248-251. IEEE, (2014)Weighted adders with selector logics for super-resolution and its FPGA-based evaluation., , and . APCCAS, page 603-606. IEEE, (2012)Clock skew estimate modeling for FPGA high-level synthesis and its application., , , and . ASICON, page 1-4. IEEE, (2015)Hardware Trojan detection and classification based on steady state learning., , and . IOLTS, page 215-220. IEEE, (2017)Muscle analysis of hand and forearm during tapping using surface electromyography., , and . GCCE, page 595-598. IEEE, (2015)A hardware-Trojan classification method utilizing boundary net structures., , and . ICCE, page 1-4. IEEE, (2018)Road-illuminance level inference across road networks based on Bayesian analysis., , and . ICCE, page 1-6. IEEE, (2018)An energy-efficient high-level synthesis algorithm for huddle-based distributed-register architectures., , and . ISCAS, page 576-579. IEEE, (2012)Robust AES circuit design for delay variation using suspicious timing error prediction., , and . ISOCC, page 101-102. IEEE, (2017)Efficient Ising Model Mapping to Solving Slot Placement Problem., , , , , , , and . ICCE, page 1-6. IEEE, (2019)