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A 25.4-to-29.5GHz 10.2mW Isolated Sub-Sampling PLL Achieving -252.9dB Jitter-Power FoM and -63dBc Reference Spur.

Z. Yang, Y. Chen, S. Yang, P. Mak, and R. Martins. ISSCC, page 270-272. IEEE, (2019)

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Yang Yang

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Sampling and Comparator Speed-Enhancement Techniques for Near-Threshold SAR ADCs.B. Hu, S. Zhang, X. Pan, X. Zhao, Z. Ding, X. Zhou, S. Yang, and Q. Li. IEEE Open J. Circuits Syst., (2021)A 0.0056mm2 all-digital MDLL using edge re-extraction, dual-ring VCOs and a 0.3mW block-sharing frequency tracking loop achieving 292fsrms Jitter and -249dB FOM.S. Yang, J. Yin, P. Mak, and R. Martins. ISSCC, page 118-120. IEEE, (2018)A 10.6-mW 26.4-GHz Dual-Loop Type-II Phase-Locked Loop Using Dynamic Frequency Detector and Phase Detector.Z. Yang, Y. Chen, S. Yang, P. Mak, and R. Martins. IEEE Access, (2020)A Compact Sub-nW/kHz Relaxation Oscillator Using a Negative-Offset Comparator With Chopping and Piecewise Charge-Acceleration in 28-nm CMOS.Y. Liu, Z. Zhu, R. Bao, J. Lin, J. Yin, Q. Li, P. Mak, and S. Yang. IEEE Trans. Circuits Syst. I Regul. Pap., 71 (2): 515-525 (February 2024)A 4.2-to-5.6 GHz Transformer-Based PMOS-only Stacked-gm VCO in 28-nm CMOS.M. Zhang, Z. Zhu, Y. Liu, Z. Zhang, R. Bao, J. Lin, H. Zhuang, J. Liu, X. Zhou, S. Yang and 1 other author(s). ICTA, page 36-37. IEEE, (2022)A 640×512 30μm Pixel Pitch 1.8mK-NETD 90.1dB-SNR Digital Read-out Integrated Circuit with Fully On-chip Image Algorithm Pixel-Level Calibration.Y. Zeng, S. Yang, Y. Liu, Z. Li, W. Huang, X. Huang, X. Zhou, J. Liu, and Q. Li. A-SSCC, page 1-3. IEEE, (2021)A 25.4-to-29.5GHz 10.2mW Isolated Sub-Sampling PLL Achieving -252.9dB Jitter-Power FoM and -63dBc Reference Spur.Z. Yang, Y. Chen, S. Yang, P. Mak, and R. Martins. ISSCC, page 270-272. IEEE, (2019)A 104μW EMI-resisting bandgap voltage reference achieving -20dB PSRR, and 5% DC shift under a 4dBm EMI level.S. Yang, P. Mak, and R. Martins. APCCAS, page 57-60. IEEE, (2014)A Low-Power RC Oscillator with Offset and Path Delay Cancellation.Y. Liu, Z. Zhu, R. Bao, S. Yang, J. Liu, X. Zhou, and Q. Li. ICTA, page 12-13. IEEE, (2021)A Low Power Sample-and-Hold Circuit with Improved Dynamic Bias for Pipelined ADC.X. Zhou, Z. Li, Y. Wang, X. Zhou, S. Yang, J. Liu, and Q. Li. APCCAS, page 189-192. IEEE, (2021)

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Disambiguation of "Yang, Shiheng"

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A 25.4-to-29.5GHz 10.2mW Isolated Sub-Sampling PLL Achieving -252.9dB Jitter-Power FoM and -63dBc Reference Spur.

Please choose a person to relate this publication to

Yang Yang

Yang Yang

Yang Yang

Yang Yang

Yang Yang

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Yang, Shiheng"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 25.4-to-29.5GHz 10.2mW Isolated Sub-Sampling PLL Achieving -252.9dB Jitter-Power FoM and -63dBc Reference Spur.

Please choose a person to relate this publication to

Yang Yang

Yang Yang

Yang Yang

Yang Yang

Yang Yang

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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URL
DOI
BibTeX
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APA
Chicago
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A 25.4-to-29.5GHz 10.2mW Isolated Sub-Sampling PLL Achieving -252.9dB Jitter-Power FoM and -63dBc Reference Spur.