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A self-checking cell logic block for fault tolerant FPGAs.

, , , , , и . ISCAS (4), стр. 477-480. IEEE, (2002)

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Daniel Re

Susanna Re

Reginaldo Ré

Johannes Marcour

Hans-Ernst Marcolin

 

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VLSI implementation of a real time fuzzy processor., , и . J. Intell. Fuzzy Syst., 6 (3): 389-401 (1998)A Power Efficient Digital Front-End for Cognitive Radio Systems., , , , и . ACSSC, стр. 199-202. IEEE, (2018)Tradeoffs between residue number system and traditional FIR filters., , и . ISCAS (2), стр. 305-308. IEEE, (2001)Compressive Sensing Reconstruction for Complex System: A Hardware/Software Approach., , , , , и . ApplePies, том 429 из Lecture Notes in Electrical Engineering, стр. 192-200. Springer, (2016)FPGA Implementation of a Low-Power QRS Extractor., , , , , , и . ApplePies, том 512 из Lecture Notes in Electrical Engineering, стр. 9-15. Springer, (2017)Efficient Ensemble Machine Learning Implementation on FPGA Using Partial Reconfiguration., , , , , , , и . ApplePies, стр. 253-259. Springer, (2018)A Reconfigurable Functional Unit for Modular Operations., , , , и . ApplePies, том 289 из Lecture Notes in Electrical Engineering, стр. 141-152. Springer, (2013)Power-delay tradeoffs in residue number system., , и . ISCAS (5), стр. 413-416. IEEE, (2003)Low-power adaptive filter based on RNS components., , , , и . ISCAS, стр. 3211-3214. IEEE, (2007)ADAPTO: full-adder based reconfigurable architecture for bit level operations., , , и . ISCAS, стр. 3434-3437. IEEE, (2008)