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Investigation and Optimization of Pin Multiplexing in High-Level Synthesis., , и . ACM Great Lakes Symposium on VLSI, стр. 427-430. ACM, (2018)Functional Obfuscation of Hardware Accelerators through Selective Partial Design Extraction onto an Embedded FPGA., , , , , , , и . ACM Great Lakes Symposium on VLSI, стр. 171-176. ACM, (2019)PEPA: Performance Enhancement of Embedded Processors through HW Accelerator Resource Sharing., и . ACM Great Lakes Symposium on VLSI, стр. 23-28. ACM, (2023)Accelerating FPGA Prototyping through Predictive Model-Based HLS Design Space Exploration., , и . DAC, стр. 97. ACM, (2019)DEEP: Dedicated Energy-Efficient Approximation for Dynamically Reconfigurable Architectures., и . ICCD, стр. 587-594. IEEE Computer Society, (2018)CERTIFY: AutomatiC MEasuRing The QualIty oF High-Level SYnthesis., , и . ISCAS, стр. 1-5. IEEE, (2023)Efficient Functional Locking of Behavioral IPs., и . MWSCAS, стр. 639-642. IEEE, (2020)Precision tunable RTL macro-modelling cycle-accurate power estimation., и . IET Comput. Digit. Tech., 5 (2): 95-103 (2011)Approximating Behavioral HW Accelerators through Selective Partial Extractions onto Synthesizable Predictive Models., и . ICCAD, стр. 1-8. ACM, (2019)Low Power Design of Runtime Reconfigurable FPGAs through Contexts Approximations., и . ICCD, стр. 524-531. IEEE, (2019)