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Disambiguation of "Beerel, Peter A."

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Testability of Asynchronous Timed Control Circuits with Delay Assumptions.

, and . DAC, page 446-451. ACM, (1991)

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Peter A Ehrl

Peter A Schmid

Peter A Wuffli

Peter A Ehrl

Peter A Gloor

 

Other publications of authors with the same name

Characterizing Sparse Connectivity Patterns in Neural Networks, , , and . (2017)cite arxiv:1711.02131Comment: Presented at the 2018 Information Theory and Applications Workshop, San Diego, California.Asynchronous Design for High-Speed and Low-Power Circuits.. PATMOS, volume 4148 of Lecture Notes in Computer Science, page 669. Springer, (2006)Neural Network Training with Approximate Logarithmic Computations., , and . ICASSP, page 3122-3126. IEEE, (2020)A polynomial time flow for implementing free-choice Petri-nets., , and . ICCD, page 227-234. IEEE Computer Society, (2012)High-performance asynchronous pipeline circuits., , and . ASYNC, page 17-28. IEEE Computer Society, (1996)High Performance Asynchronous ASIC Back-End Design Flow Using Single-Track Full-Buffer Standard Cells., , and . ASYNC, page 95-105. IEEE Computer Society, (2004)Design and Analysis of Testable Mutual Exclusion Elements., , , , , , and . ASYNC, page 124-131. IEEE Computer Society, (2015)Analysis and Design of Delay Lines for Dynamic Voltage Scaling Applications., , , , , and . ASYNC, page 11-18. IEEE Computer Society, (2016)Blade - A Timing Violation Resilient Asynchronous Template., , , , , , , , , and . ASYNC, page 21-28. IEEE Computer Society, (2015)Deep-n-Cheap: An Automated Search Framework for Low Complexity Deep Learning., , , and . ACML, volume 129 of Proceedings of Machine Learning Research, page 273-288. PMLR, (2020)