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Disambiguation of "Hodjat, Alireza"

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Reconfigurable Architectures for Curve-Based Cryptography on Embedded Micro-Controllers.

, , , , and . FPL, page 1-4. IEEE, (2006)

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Mahshid Hodjat

Hodjat Rahmati

Hodjat Shekarriz Foumani

Alireza Djirsarai

Alireza Rahimi

 

Other publications of authors with the same name

A Scalable and High Performance Elliptic Curve Processor with Resistance to Timing Attacks., , and . ITCC (1), page 538-543. IEEE Computer Society, (2005)Testing ThumbPod: Softcore bugs are hard to find., , , , , , , and . HLDVT, page 77-82. IEEE Computer Society, (2003)Design flow for HW / SW acceleration transparency in the thumbpod secure embedded system., , , , , , , and . DAC, page 60-65. ACM, (2003)HW/SW co-design of a hyperelliptic curve cryptosystem using a microcode instruction set coprocessor., , , and . Integr., 40 (1): 45-51 (2007)AES-Based Security Coprocessor IC in 0.18-$muhbox m$CMOS With Resistance to Differential Power Analysis Side-Channel Attacks., , , , , , and . IEEE J. Solid State Circuits, 41 (4): 781-792 (2006)A side-channel leakage free coprocessor IC in 0.18µm CMOS for embedded AES-based cryptographic and biometric processing., , , , , , and . DAC, page 222-227. ACM, (2005)Reconfigurable Architectures for Curve-Based Cryptography on Embedded Micro-Controllers., , , , and . FPL, page 1-4. IEEE, (2006)Area-Throughput Trade-Offs for Fully Pipelined 30 to 70 Gbits/s AES Processors., and . IEEE Trans. Computers, 55 (4): 366-372 (2006)Architectural Design Features of a Programmable High Throughput AES Coprocessor., , and . ITCC (2), page 498-502. IEEE Computer Society, (2004)isbn: 0-7695-2108-8.Minimum Area Cost for a 30 to 70 Gbits/s AES Processor., and . ISVLSI, page 83-88. IEEE Computer Society, (2004)