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Hardware-Assisted Simulation and Evaluation of IP Cores Using FPGA-Based Rapid Prototyping Boards.

, and . IEEE International Workshop on Rapid System Prototyping, page 96-102. IEEE Computer Society, (2004)

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Distribution of Bitstream-Level IP Cores for Functional Evaluation Using FPGAs.. FPL, volume 3203 of Lecture Notes in Computer Science, page 700-709. Springer, (2004)Hardware-Assisted Simulation and Evaluation of IP Cores Using FPGA-Based Rapid Prototyping Boards., and . IEEE International Workshop on Rapid System Prototyping, page 96-102. IEEE Computer Society, (2004)A Run-Time Reconfigurable Hardware Infrastructure for IP-Core Evaluation and Test.. FPL, page 505-508. IEEE, (2005)Platform Development for Run-Time Reconfigurable Co-Emulation.. IEEE International Workshop on Rapid System Prototyping, page 179-185. IEEE Computer Society, (2006)