Author of the publication

A unique and robust single slice FPGA identification generator.

, , and . ISCAS, page 1223-1226. IEEE, (2014)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Improving the Security of Dual-Rail Circuits., , , and . CHES, volume 3156 of Lecture Notes in Computer Science, page 282-297. Springer, (2004)Standard cell and full custom power-balanced logic : ASIC implementation.. University of Newcastle Upon Tyne, UK, (2008)British Library, EThOS.Power-balanced asynchronous logic., and . ECCTD, page 213-216. IEEE, (2005)A unique and robust single slice FPGA identification generator., , and . ISCAS, page 1223-1226. IEEE, (2014)Self-Timed Physically Unclonable Functions., , , , , and . NTMS, page 1-5. IEEE, (2012)Asynchronous Physical Unclonable Functions - AsyncPUF.. MCSS, volume 287 of Communications in Computer and Information Science, page 230-241. Springer, (2012)Clockless Physical Unclonable Functions.. TRUST, volume 7344 of Lecture Notes in Computer Science, page 110-121. Springer, (2012)Power-Balanced Self Checking Circuits for Cryptographic Chips., , and . IOLTS, page 157-162. IEEE Computer Society, (2005)