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COMPACTEST: A Method to Generate Compact Test Sets for Combinatorial Circuits., , and . ITC, page 194-203. IEEE Computer Society, (1991)OWARU: Free Space-Aware Timing-Driven Incremental Placement With Critical Path Smoothing., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 37 (9): 1825-1838 (2018)OWARU: free space-aware timing-driven incremental placement., , , , and . ICCAD, page 8. ACM, (2016)Transformational Placement and Synthesis., , , , , , and . DATE, page 194-201. IEEE Computer Society / ACM, (2000)Design methodology for the IBM POWER7 microprocessor., , , , , , , , , and 15 other author(s). IBM J. Res. Dev., 55 (3): 9 (2011)Design Rule Violation Prediction at Sub-10-nm Process Nodes Using Customized Convolutional Networks., , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (10): 3503-3514 (2022)Depth controlled symmetric function fanin tree restructure., , , and . ICCAD, page 585-591. IEEE, (2013)Early Scenario Pruning for Efficient Design Space Exploration in Physical Synthesis., , , and . VLSID, page 116-121. IEEE Computer Society, (2016)Logical and physical restructuring of fan-in trees., , , , , and . ISPD, page 67-74. ACM, (2010)SPADES: a simulator for path delay faults in sequential circuits., , and . EURO-DAC, page 428-435. IEEE Computer Society Press, (1992)