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A sub-μW bio-potential front end in 65nm CMOS., , , and . VLSI-SoC, page 1-4. IEEE, (2017)A 93% Peak Efficiency Fully-Integrated Multilevel Multistate Hybrid DC-DC Converter., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 65-I (8): 2617-2630 (2018)Numerical analysis of nano schottky junctions for developing novel sub-20 nm electronic devices., , and . ICECS, page 502-505. IEEE, (2014)High Throughput Architecture for High Performance NoC., , and . ISCAS, page 2241-2244. IEEE, (2009)A single-chip CMOS front-end receiver architecture for multi-standard wireless applications., and . ISCAS (4), page 374-377. IEEE, (2001)A reconfigurable low IF-zero IF receiver architecture for multi-standard wide area wireless networks., , and . ICECS, page 934-937. IEEE, (2003)Power efficient Networks on Chip., , , and . ICECS, page 105-108. IEEE, (2009)Accurate modeling of simultaneous switching noise in low voltage digital VLSI., , , and . ISCAS (6), page 210-213. IEEE, (1999)High throughput architecture for CLICHÉ Network on Chip., , and . SoCC, page 155-158. IEEE, (2009)A low voltage CMOS class AB operational transconductance amplifier., , , and . ISCAS (2), page 632-635. IEEE, (1999)