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Utilizing Reuse Information in Data Cache Management., , , , and . International Conference on Supercomputing, page 449-456. ACM, (1998)Improving Execution Time of Parallel Programs on Large Scale Chip Multiprocessors with Constant Average Power Processing., , , , and . ICCD, page 649-652. IEEE Computer Society, (2017)Techniques for extracting instruction level parallelism on MIMD architectures., and . MICRO, page 128-137. ACM / IEEE Computer Society, (1993)MISC: a Multiple Instruction Stream Computer., , and . MICRO, page 193-196. ACM / IEEE Computer Society, (1992)A modified approach to data cache management., , , and . MICRO, page 93-103. ACM / IEEE Computer Society, (1995)Improving Provisioned Power Efficiency in HPC Systems with GPU-CAPP., , , , and . HiPC, page 112-122. IEEE, (2018)Strategies for Achieving Improved Processor Throughput., and . ISCA, page 362-369. ACM, (1991)Dynamic Base Register Caching: A Technique for Reducing Address Bus Width., and . ISCA, page 128-137. ACM, (1991)A Study of Single-Chip Processor/Cache Organizations for Large Numbers of Transistors., , and . ISCA, page 338-347. IEEE Computer Society, (1994)Analysis of the effect of core affinity on high-throughput flows., , , , , , and . NDM@SC, page 9-15. IEEE, (2014)