( en | de | ru )

 

Disambiguation of "Naffziger, Samuel"

Author of the publication

copydeleteadd this publication to your clipboard
Pioneering Chiplet Technology and Design for the AMD EPYC™ and Ryzen™ Processor Families : Industrial Product.

, , , , , , and . ISCA, page 57-70. IEEE, (2021)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Samuel Taddese

Samuel Sossalla

Samuel Buttenwieser

Samuel Glasscheib

Samuel Cydulka

 

Other publications of authors with the same name

A New Era of Tailored Computing., , , and . VLSI Circuits, page 1-2. IEEE, (2021)5.6 Adaptive clocking system for improved power efficiency in a 28nm x86-64 microprocessor., , , and . ISSCC, page 106-107. IEEE, (2014)Welcome program chairs., and . Hot Chips Symposium, page 1-2. IEEE, (2014)Unified Power Frequency Model Framework., , , , , and . ISLPED, page 174-179. ACM, (2016)8.4 Radeon RX 5700 Series: The AMD 7nm Energy-Efficient High-Performance GPUs., , , , , , and . ISSCC, page 150-152. IEEE, (2020)A 90-nm variable frequency clock system for a power-managed itanium architecture processor., , , , and . IEEE J. Solid State Circuits, 41 (1): 218-228 (2006)Design of the Two-Core x86-64 AMD "Bulldozer" Module in 32 nm SOI CMOS., , , , , , , , and . IEEE J. Solid State Circuits, 47 (1): 164-176 (2012)'Zeppelin': An SoC for multichip architectures., , , and . ISSCC, page 40-42. IEEE, (2018)Understanding Chiplets Today to Anticipate Future Integration Opportunities and Limits., , and . DATE, page 142-145. IEEE, (2021)3D V-Cache: the Implementation of a Hybrid-Bonded 64MB Stacked Cache for a 7nm x86-64 CPU., , , , , , , , , and . ISSCC, page 428-429. IEEE, (2022)