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Disambiguation of "Pechanek, Gerald G."

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An introduction to an array memory processor for application specific acceleration.

, and . HPEC, page 1-7. IEEE, (2017)

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Giuseppe G G Manzardo

G Wahl

G Bol

G Sawers

G Hübner

 

Other publications of authors with the same name

ManArray Processor Interconnection Network: An Introduction., , and . Euro-Par, volume 1685 of Lecture Notes in Computer Science, page 761-765. Springer, (1999)Architectural simulation system for M.f.a.s.t., and . Annual Simulation Symposium, page 221-. IEEE Computer Society, (1996)A neuro-emulator with learning and virtual emulation capabilities., , , , and . ICNN, page 1355-1360. IEEE, (1996)An introduction to an array memory processor for application specific acceleration., and . HPEC, page 1-7. IEEE, (2017)The Sum-Absolute-Difference Motion Estimation Accelerato., , , and . EUROMICRO, page 20559-20566. IEEE Computer Society, (1998)A Neuro-Architecture with Embedded Learning., , , , and . Parallel and Distributed Computing and Systems, page 103-106. IASTED/ACTA Press, (1995)A massively parallel diagonal-fold array processor., , and . ASAP, page 140-143. IEEE, (1993)SPIN: a sequential pipelined neurocomputer., , and . ICTAI, page 74-81. IEEE Computer Society, (1991)The ManArray( Embedded Processor Architecture., and . EUROMICRO, page 1348-1355. IEEE Computer Society, (2000)Digital neural emulators using tree accumulation and communication structures., , and . IEEE Trans. Neural Networks, 3 (6): 934-950 (1992)