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An Energy-Efficient Cardiac Arrhythmia Classification Processor using Heartbeat Difference based Classification and Event-Driven Neural Network Computation with Adaptive Wake-Up.

J. Liu, J. Xiao, J. Fan, Q. Liu, Z. Zhu, S. Li, Z. Zhang, S. Yang, W. Shan, S. Lin, L. Chang, L. Zhou, and J. Zhou. CICC, page 1-2. IEEE, (2022)

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Weiwei Tian

Weiwei Chen

Shan-Shan Zhan

Weiwei Cheng

Weiwei Wang

Other publications of authors with the same name

HTD: A light-weight holosymmetrical transition detector based in-situ timing monitoring technique for wide-voltage-range in 40nm CMOS.W. Dai, W. Shan, X. Liu, and J. Yang. A-SSCC, page 209-212. IEEE, (2017)A 0.44V-1.1V 9-transistor transition-detector and half-path error detection technique for low power applications.X. Shang, W. Shan, L. Shi, X. Wan, and J. Yang. A-SSCC, page 205-208. IEEE, (2017)A 0.46V-1.1V Transition-Detector with In-Situ Timing-Error Detection and Correction Based on Pulsed-Latch Design in AES Accelerator.X. Shang, W. Shan, J. Xu, M. Lu, Y. Xiang, L. Shi, and J. Yang. A-SSCC, page 1-4. IEEE, (2018)A Depthwise Separable Convolution Neural Network for Small-footprint Keyword Spotting Using Approximate MAC Unit and Streaming Convolution Reuse.Y. Lu, W. Shan, and J. Xu. APCCAS, page 309-312. IEEE, (2019)An Efficient and Reliable Negative Margin Timing Error Detection for Neural Network Accelerator without Accuracy Loss in 28nm CMOS.Z. Li, W. Shan, C. Wu, H. Ge, and J. Yang. A-SSCC, page 1-3. IEEE, (2021)Short-path Padding Method for Timing Error Resilient Circuits based on Transmission Gates Insertion.W. Dai, P. Liu, and W. Shan. ACM Great Lakes Symposium on VLSI, page 105-110. ACM, (2018)IVATS: A Leakage Reduction Technique Based on Input Vector Analysis and Transistor Stacking in CMOS Circuits.L. Deng, K. Li, and W. Shan. ISCAS, page 1-5. IEEE, (2023)VLSI design of a reconfigurable S-box based on memory sharing method.W. Shan, X. Zhang, X. Fu, and P. Cao. IEICE Electron. Express, 11 (1): 20130872 (2014)A Side-channel Analysis Resistant Reconfigurable Cryptographic Coprocessor Supporting Multiple Block Cipher Algorithms.W. Shan, L. Shi, X. Fu, X. Zhang, C. Tian, Z. Xu, J. Yang, and J. Li. DAC, page 176:1-176:6. ACM, (2014)Multi-Task Evolutionary to PVT Knowledge Transfer for Analog Integrated Circuit Optimization.J. Li, H. Zhi, W. Shan, Y. Li, Y. Zeng, and Y. Li. ICCAD, page 1-9. IEEE, (2023)

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Disambiguation of "Shan, Weiwei"