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Improving the Accuracy in SpMV Implementation Selection with Machine Learning., , , , and . CANDAR (Workshops), page 172-177. IEEE, (2020)A memory bank conflict prevention mechanism for SYCL on SX-Aurora TSUBASA., , , and . CANDAR (Workshops), page 217-222. IEEE, (2021)A Directive Generation Approach Using User-Defined Rules., , , and . CANDAR, page 515-521. IEEE Computer Society, (2016)Designing an Open Database of System-Aware Code Optimizations., , and . CANDAR, page 369-374. IEEE Computer Society, (2017)Spatiotemporal Anomaly Detection for Large-Scale Sensor Data., , and . PAAP, page 162-168. IEEE, (2021)Enhancing Memory Bandwidth in a Single Stream Computation with Multiple FPGAs., , and . FPT, page 378-380. IEEE, (2018)Design and evaluation of a media-oriented vector processor with a multi-banked cache memory., , , , and . ESTIMedia, page 78-87. IEEE, (2013)A media-oriented vector architectural extension with a high bandwidth cache system., , , , and . COOL Chips, page 1-3. IEEE Computer Society, (2012)A cache partitioning mechanism to protect shared data for CMPs., , , , and . COOL Chips, page 1-2. IEEE Computer Society, (2016)3D on-chip memory for the vector architecture., , , and . 3DIC, page 1-6. IEEE, (2009)