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Ping-Pong Mesh: A New Resonant Clock Design for Surge Current and Area Overhead Reduction.

, , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 36 (1): 146-155 (2017)

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Analysis and mitigation of NBTI-induced performance degradation for power-gated circuits., , , and . ISLPED, page 139-144. IEEE/ACM, (2011)Power reduction through iterative gate sizing and voltage scaling., , , and . ISCAS (1), page 246-249. IEEE, (1999)Accelerating Pattern Matching Using a Novel Parallel Algorithm on GPUs., , , and . IEEE Trans. Computers, 62 (10): 1906-1916 (2013)Overoptimistic voltage scaling in pre-error AVS systems and learning-based alleviation., , , , , and . SoCC, page 350-355. IEEE, (2016)Gate-Level Design Exploiting Dual Supply Voltages for Power-Driven Applications., , , and . DAC, page 68-71. ACM Press, (1999)Concurrency-oriented SoC re-certification by reusing block-level test vectors., , , and . ISQED, page 140-147. IEEE, (2014)Electromigration and voltage drop aware power grid optimization for power gated ICs., , and . ISLPED, page 391-394. ACM, (2007)A novel low-cost dynamic logic reconfigurable structure strategy for low power optimization., , , , and . ASP-DAC, page 250-255. IEEE, (2016)NBTI-aware power gating design., , , and . ASP-DAC, page 609-614. IEEE, (2011)Low-power timing closure methodology for ultra-low voltage designs., , , , , and . ICCAD, page 697-704. IEEE, (2013)