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Disambiguation of "Chen, Yongzhen"

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A quadrature clock generator with calibration for 22∼31.4 GS/s real-time sampling system.

, , , , , , and . ESSCIRC, page 136-139. IEEE, (2015)

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Chen Chen

Chen Chen

Shih Chen Chen

Yi-Chen Chen

Chen-Loung Chen

 

Other publications of authors with the same name

An Operational Amplifier Assisted Input Buffer and An Improved Bootstrapped Switch for High-Speed and High-Resolution ADCs., , , , and . ISCAS, page 1-5. IEEE, (2018)A 12-Bit ENOB 8MHz BW Noise-Shaping SAR ADC Using High-Speed Switches., , , , and . MWSCAS, page 392-395. IEEE, (2018)A 625MS/s, 12-Bit, SAR Assisted Pipeline ADC with Effective Gain Analysis for Inter-stage Ringamps., , , , , , and . ESSCIRC, page 197-200. IEEE, (2019)An Input Buffer for 4 GS/s 14-b Time-Interleaved ADC., , , , and . ASICON, page 1-4. IEEE, (2021)A 4.75-64 Gb/s PAM-4 Wireline Transmitter with 3-tap FFE in 28-nm CMOS., , , , , and . ISCAS, page 1-5. IEEE, (2023)A proved dither-injection method for memory effect in double sampling pipelined ADC., , , , and . ASICON, page 754-757. IEEE, (2017)A Current-Mode, 30 dB Range with 0.5 dB Step, 0.1 to 6 GHz Attenuator for Wideband Receiver., , , , and . MWSCAS, page 1-4. IEEE, (2022)An improved ring amplifier with process- and supply voltage-insensitive dead-zone., , , , and . MWSCAS, page 811-814. IEEE, (2017)A 32GS/s 7bit TI-SAR ADC in 28nm for 32Gb/s ADC-Based SerDes Receiver., , , , and . ASICON, page 1-4. IEEE, (2023)Physical Coding Sublayer For 32Gbps SerDes Based On JESD204C., , , , and . ASICON, page 1-4. IEEE, (2021)