( en | de | ru )

 

Disambiguation of "Koibuchi, Michihiro"

Author of the publication

copydeleteadd this publication to your clipboard
Low-latency wireless 3D NoCs via randomized shortcut chips.

, , , , , , , , and . DATE, page 1-6. European Design and Automation Association, (2014)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Michihiro Saito

 

Other publications of authors with the same name

The Impact of Application Mapping on Non-Random and Random Network Topologies., and . ISPA/BDCloud/SocialCom/SustainCom, page 16-25. IEEE, (2019)Designing High-Performance Interconnection Networks with Host-Switch Graphs., , , , and . IEEE Trans. Parallel Distributed Syst., 30 (2): 315-330 (2019)SINET5: A low-latency and high-bandwidth backbone network for SDN/NFV Era., , , , , , , , , and 1 other author(s). ICC, page 1-7. IEEE, (2017)A link removal methodology for Networks-on-Chip on reconfigurable systems., , , and . FPL, page 269-274. IEEE, (2008)AxNoC: Low-power Approximate Network-on-Chips using Critical-Path Isolation., , , , and . NOCS, page 6:1-6:8. IEEE, (2018)A Virtual-Channel Free Mapping for Application-Specific On-Chip Torus Networks., , and . PDCS, page 24-31. ISCA, (2006)Scalable Low-Latency Inter-FPGA Networks., , , , and . IPDPS, page 234-245. IEEE, (2022)Message from the Organizers: CANDAR 2022., , , and . CANDAR, page viii. IEEE, (2022)Layout-conscious random topologies for HPC off-chip interconnects., , , and . HPCA, page 484-495. IEEE Computer Society, (2013)Routing Algorithms Based on 2D Turn Model for Irregular Networks., , , and . ISPAN, page 289-294. IEEE Computer Society, (2002)